`timescale 1ns / 1ps 
module tb();
    reg rst, clk;    
    reg [1:0] work_state; 
    wire sop, eop, vld;
    wire [31:0] data; 


    initial begin            
        $dumpfile("tb.vcd");        
        $dumpvars(0, tb);    
    end

    initial begin
        rst = 1;
        clk = 1;
        forever begin
            #10 clk = ~clk;
        end
    end


    initial begin
        #30
        rst <= 0;
    end

    initial
        #200000000 $finish;

    dataLoader loader(.clk(clk), .rst(rst), 
                    .sop(sop), .eop(eop), .vld(vld), .data(data));
endmodule